This application claims the priority benefit of Taiwan application serial no. 90102142, filed Feb. 2, 2001.
1. Field of Invention
The present invention relates to a technique of manufacturing a photo-electric thin film transistor. More particularly, the present invention relates to a poly-silicon thin film transistor with a self-alignment ability.
2. Description of Related Art
A monitor is a kind of popular device in our daily file, especially for the television and the computer to display images. Typically, the monitor is constructed by a cathode-ray tube, a relatively large space is necessary for assembling a monitor with the cathode-ray tube. Undoubtedly, it is impossible to assemble a laptop with a cathode-ray-tube monitor. Therefore, a plane-display monitor with the dot-matrix design such as a think film transistor liquid crystal display (TFT-LCD) is developed. In the plane-display monitor, pixels of an image arc respectively controlled by thin film transistors.
The structure of a thin film transistor is different from that of a metal oxide semiconductor (MOS). FIGS. 1A through 1E are schematic, cross-sectional views of the conventional method for manufacturing a thin film transistor.
As shown in FIG. 1A, an amorphous silicon 102 is formed on a transparent substrate 100. The amorphous silicon 102 is convened into the polysilicon layer by performing a laser annealing process 104. The polysilicon converted from the amorphous silicon 102 is labeled as a polysilicon 106 (as shown in FIG. 1B).
As shown in FIG. 1B, a gate oxide layer 108 is formed on the polysilicon 106. A gate electrode layer 110 is formed on the gate oxide layer 108.
As shown in FIG. 1C, an implantation process 112 is performed to implant doped ions such as N-type doped ions into the polysilicon 106 and to form a doped region 106a in the polysilicon layer 106 by using the gate electrode 110 as a mask.
As shown in FIG. 1D, the gate electrode 110 is patterned to be shrank into a gate electrode 110a with a relatively small width in order to extend the region 116 between the doped region 106a and the gate electrode 110a. A plasma hydrogenation process (not shown) is performed to compensate the dangling silicon bond in the polysilicon 106.
As shown in FIG. 1E, a metal layer (not shown) is formed over the substrate 100. The metal layer is patterned to form a metal pad 118 on the doped region 106a. 
In the conventional process described above, in order to enlarge the region 116, it is necessary to perform an additional photolithography process to pattern the gate electrode 110. Moreover, if the misalignment happens during performing the additional photolithography process, the region 116 at both side of the gate electrode 110a is uneven. Typically, an additional implantation process and annealing process is performed after the gate electrode 110a is formed to form lightly doped region in region 116. Furthermore, the laser annealing process 104 and plasma hydrogenation process are performed individually. Therefore, the process procedures are very complex and the cost is high.
The invention provides a thin film transistor. The thin film transistor comprises a substrate, a dielectric layer and a polysilicon layer. A gate electrode is located on the substrate. A dielectric layer is located on the substrate and the gate electrode. A polysilicon layer is located on the dielectric layer. The polysilicon layer comprises a channel region and a doped region, wherein the channel region is located above the gate electrode and the doped region is adjacent to the channel region.
The invention provides a method of manufacturing a thin firm transistor. A substrate having a gate electrode formed thereon is provided. A gate dielectric layer, an amorphous silicon layer, a silicon-bond-protection layer and a photoresist layer are formed over the substrate in sequence. The silicon-bond-protection dielectric layer comprises elements for compensating dangling silicon bonds. The photoresist layer is patterned by using the gate electrode as a mask and by exposuring the photoresist layer from the bottom of the substrate. A thermal reflow process is performed to laterally extend the patterned photoresist. The bottom of the soften photoresist is larger than the gate electrode. A portion of the silicon-bond protection layer is removed to expose a portion of the amorphous silicon layer by using the photoresist as a mask. A doped dielectric layer is formed over the substrate. A thermal annealing process is performed to convert silicon the amorphous layer into a polysilicon layer. Simultaneously, dopants in the doped doelectric layer diffuse into the polysilicon layer to form a doped region and elements in the silicon-bond-protection layer diffuse into the polysilicon layer to form a channel region. The silicon-bond-protection layer and the doped dielectric layer are removed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.